(1) Field of the Invention
The present invention relates to a structure of a semiconductor device in which, for example, a plurality of semiconductor chips and ascribe grid are formed on a wafer-shaped substrate. In particular, the present invention relates to structures of electrode pads provided on such semiconductor chip and scribe grid.
(2) Description of the Related Art
Conventionally, there is manufactured a semiconductor device having a structure in which, for example, a plurality of semiconductor chips, each having a semiconductor circuit integrated thereon, and a scribe grid are formed on a wafer-shaped substrate. Herein, a region called the scribe grid is used as a “spacing” along which the wafer is cut to obtain a semiconductor circuit as a semiconductor chip. In order to determine whether or not the semiconductor circuit in the semiconductor chip is formed without fail, a plurality of elements called process control modules (hereinafter, referred to as “scribe PCMs”) are formed on the scribe grid.
Hereinafter, a description will be given of a conventional semiconductor device (refer to, e.g., JP2001-332577A) with reference to the drawings.
FIGS. 4A to 4C specifically illustrate a semiconductor chip and a scribe PCM formed on a wafer in the conventional semiconductor device. At present, a semiconductor device is typically formed into a wafer shape as illustrated in FIG. 4A. Normally, a plurality of semiconductor chips 2, each having a semiconductor circuit integrated thereon, are formed on a wafer 1 through a manufacturing process called a diffusion process. Thereafter, as illustrated in FIG. 4B, each semiconductor chip 2 is cut out from the wafer 1, and then is subjected to packaging and the like; accordingly, a chip-shaped semiconductor integrated circuit (LSI) is manufactured. Herein, as illustrated in FIG. 4C, a plurality of scribe PCMs 4 are formed on a scribe grid 3.
Each scribe PCM 4 includes multilayered electrode pads 5 for external electrical connection. Formation of such scribe PCM 4 on the scribe grid 3 makes it possible to examine quality of the semiconductor device as the entire wafer 1, particularly, electrical quality thereof. Although not illustrated in the drawings, a plurality of multilayered electrode pads for external electrical connection are also provided on each semiconductor chip 2.
FIGS. 5A to 5D are sectional views each illustrating a process for forming bumps on an electrode pad 5 of a scribe PCM 4 formed on the scribe grid 3 and an electrode pad 6 of a semiconductor chip 2, respectively, by electroless plating in the conventional semiconductor device. As an example, the drawings show that the semiconductor device has a multilayer structure of three wiring layers.
As illustrated in FIG. 5A, three electrode pads 5 (6) are laminated in a vertical direction. Herein, the uppermost one of the three electrode pads 5 (6) is made of Al. In FIG. 5A, the electrode pad 5 of the scribe PCM 4 is illustrated on a left side and the electrode pad 6 of the semiconductor chip 2 is illustrated on a right side.
First, as illustrated in FIG. 5B, Zn plating is performed in an electroless manner. Thus, Zn plating layers 7 are formed on the electrode pad 5 of the scribe PCM 4 and the electrode pad 6 of the semiconductor chip 2, respectively. A mechanism of the Zn plating is as follows. That is, Al which is a material for the electrode pad 5 (6) is dissolved in an electroless Zn plating solution as Al ions 6a with difference in ionization tendency between Al and Zn (ionization tendency: Al>Zn). Then, Zn ions 7a in the electroless Zn plating solution are deposited on the electrode pad 5 (6); thus, the Zn plating layer 7 is formed. In other words, displacement plating is performed herein.
Next, as illustrated in FIG. 5C, Ni plating is performed in an electroless manner. Thus, Ni bumps 8 are formed on the Zn plating layer 7 of the electrode pad 5 of the scribe PCM 4 and the Zn plating layer 7 of the electrode pad 6 of the semiconductor chip 2, respectively. A mechanism of the Ni plating is as follows. That is, Zn in the Zn plating layer 7 is dissolved in an electroless Ni plating solution as Zn ions 7a with difference in ionization tendency between Zn and Ni (ionization tendency: Zn>Ni). Then, Ni ions 8a in the electroless Ni plating solution are deposited on the Zn plating layer 7; thus, the Ni bump 8 is formed. In other words, displacement plating is performed herein.
Next, as illustrated in FIG. 5D, Au plating is performed in an electroless manner. Thus, Au plating layers 9 are formed on the Ni bump 8 of the electrode pad 5 of the scribe PCM 4 and the Ni bump 8 of the electrode pad 6 of the semiconductor chip 2, respectively. A mechanism of the Au plating is as follows. That is, Ni in the Ni bump 8 is dissolved in an electroless Au plating solution as Ni ions 8a with difference in ionization tendency between Ni and Au (ionization tendency: Ni>Au). Then, Au ions 9a in the electroless Au plating solution are deposited on the Ni bump 8; thus, the Au plating layer 9 is formed. In other words, displacement plating is performed herein.
FIG. 6 specifically illustrates an electroless plating method performed on the conventional semiconductor device illustrated in FIGS. 5B to 5D. A mechanism of the electroless plating method is as follows. That is, the metal material for the electrode pad 5 of the scribe PCM 4 and the electrode pad 6 of the semiconductor chip 2 is dissolved in a plating solution 13 (herein, a Zn plating solution, a Ni plating solution or an Au plating solution) as metal ions 14 (herein, Al ions, Zn ions or Ni ions) with difference in ionization tendency (ionization tendency: Al>Zn>Ni>Au). Then, metal ions 15 (herein, Zn ions, Ni ions or Au ions) in the plating solution 13 are deposited on the electrode pad 5 of the scribe PCM 4 and the electrode pad 6 of the semiconductor chip 2; thus, a plating layer (herein, a Zn plating layer, a Ni plating layer or an Au plating layer) is formed.
FIGS. 7A and 7B are sectional views each illustrating a dicing process for cutting the electrode pad 5 of the scribe PCM 4 with a bump formed on the electrode pad 5 as illustrated in FIG. 5D, thereby to obtain a semiconductor chip 2 from the wafer 1.
As illustrated in FIG. 7A, the scribe grid 3 (together with the scribe PCM 4, the electrode pad 5 of the scribe PCM 4, and the Ni bump 8 and the Au plating layer 9 on the electrode pad 5) is cut by means of a dicing cutter 10. Thus, as illustrated in FIG. 7B, a semiconductor chip 2 can be cut out from the wafer 1.
In the conventional semiconductor device, however, the structure of the electrode pad 5 illustrated in FIG. 5D causes the following problems.
FIGS. 8A and 8B are sectional views each illustrating a dicing process for cutting the electrode pad 5 of the scribe PCM 4 with a bump formed on the electrode pad 5 as illustrated in FIG. 5D, thereby to obtain a semiconductor chip 2 from the wafer 1, similarly to FIGS. 7A and 7B. As illustrated in FIG. 8A, the scribe grid 3 (together with the scribe PCM 4, the electrode pad 5 of the scribe PCM 4, and the Ni bump 8 and the Au plating layer 9 on the electrode pad 5) is cut by means of the dicing cutter 10.
If the dicing cutter 10 deviates from an appropriate position as illustrated in FIG. 8A, an abnormal state occurs as illustrated in FIG. 8B. Specifically, the Ni bump 8 and the like are partially left at an edge portion even after the dicing process. If the conductive Ni bump 8 is left at the edge portion, electrical leakage may occur at the “left bump” in a case where the semiconductor chip 2 is subjected to packaging subsequently.
FIG. 9 is a sectional view illustrating a dicing process for cutting the electrode pad 5 of the scribe PCM 4 with a bump formed on the electrode pad 5 as illustrated in FIG. 5D, thereby to obtain a semiconductor chip 2 from the wafer 1, similarly to FIGS. 8A and 8B. As illustrated in FIG. 9, the scribe grid 3 (together with the scribe PCM 4, the electrode pad 5 of the scribe PCM 4, and the Ni bump 8 and the Au plating layer 9 on the electrode pad 5) is cut by means of a dicing cutter 10. The dicing cutter 10 used herein has a large width in order to prevent the bump from being partially left at an edge portion.
Thus, it is possible to prevent the bump 8 from being partially left at the edge portion. However, since the width of the dicing cutter 10, that is, a width of a “spacing” becomes large, the scribe grid 3 must be made larger in width in conjunction. As a result, the scribe grid 3 formed on the wafer 1 is larger in width than the aforementioned scribe grid 3 illustrated in FIG. 7A (a lower side of FIG. 9). Consequently, an area for formation of semiconductor chips 2 is disadvantageously decreased in the wafer 1, so that there is a possibility that semiconductor chips 2 to be obtained from one wafer are reduced in number.